16550


D₀	1 •	40	Vcc
D₁	2	39	RI
D₂	3	38	DCD
D₃	4	37	DSR
D₄	5	36	CTS
D₅	6	35	MR
D₆	7	34	OUT1
D₇	8	33	DTR
RCLK	9	32	RTS
RX	10	31	OUT2
TX	11	30	INTR
CS0	12	29	RXRDY
CS1	13	28	A₀
CS2	14	27	A₁
BAUDOUT	15	26	A₂
XIN	16	25	ADS
XOUT	17	24	TXRDY
WR	18	23	DDIS
WR	19	22	RD
GND	20	21	RD

Pin	Symbol	Description
1	D₀	data bus
2	D₁	data bus
3	D₂	data bus
4	D₃	data bus
5	D₄	data bus
6	D₅	data bus
7	D₆	data bus
8	D₇	data bus
9	RCLK	receiver clock input (16x baud rate)
10	RX	serial input
11	TX	serial output
12	CS0	chip select (active high)
13	CS1	chip select (active high)
14	CS2	chip select (active low)
15	BAUDOUT	baud rate generator output
16	XIN	external crystal input
17	XOUT	external crystal output
18	WR	write enable (active low)
19	WR	write enable (active high)
20	GND	ground
21	RD	read enable (active low)
22	RD	read enable (active high)
23	DDIS	driver disable
24	TXRDY	TX DMA signal
25	ADS	address strobe input
26	A₂	register select
27	A₁	register select
28	A₀	register select
29	RXRDY	RX DMA signal
30	INTR	interrupt output (active high)
31	OUT2	general purpose output
32	RTS	request to send (output to modem)
33	DTR	data terminal ready (output to modem)
34	OUT1	general purpose output
35	MR	master reset (active high)
36	CTS	clear to send (input from modem)
37	DSR	data set ready (input from modem)
38	DCD	data carrier detect (input from modem)
39	RI	ring indicator (input from modem)
40	Vcc	supply voltage

Parameter	Value	Unit
maximum baud rate	1.5	Mbaud

Notes

Register 000: receive buffer (read), transmit holding register (write)
Register 001: interrupt enable
Register 010: interrupt identification (read), FIFO control (write)
Register 011: line control
Register 100: modem control
Register 101: line status
Register 110: modem status
Register 111: scratch register
When bit 7 in the Line Control Register is set, the baud rate divisor latch is enabled. (register 000=LSB, register 001=MSB)

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

Universal asynchronous receiver-transmitter with FIFOs

Specifications

Notes