4526

Programmable 4-bit binary down counter


Q3	1 •	16	Vcc
P3	2	15	Q2
PL	3	14	P2
CP1	4	13	CF
P0	5	12	TC
CP0	6	11	P1
Q0	7	10	MR
GND	8	9	Q1

Pin	Symbol	Description
1	Q3	count output
2	P3	parallel input
3	PL	parallel load (active high)
4	CP1	clock input (high-to-low triggered)
5	P0	parallel input
6	CP0	clock input (low-to-high triggered)
7	Q0	count output
8	GND	ground
9	Q1	count output
10	MR	asynchronous master reset (active high)
11	P1	parallel input
12	TC	terminal count output
13	CF	cascade feedback input
14	P2	parallel input
15	Q2	count output
16	Vcc	supply voltage

Notes

When CP1 is low, the counter advances on a low-to-high transition of CP0.
When CP0 is high, the counter advances on a high-to-low transition of CP1.
TC goes high when the count is 0, CF is high, and PL is low.
For a single-stage divide-by-n circuit, connect the TC output to PL and set the P0-P3 inputs to n.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.