4557

1-to-64 bit variable length shift register


L₂	1 •	16	Vcc
L₁	2	15	L₄
MR	3	14	L₈
CP₀	4	13	L₁₆
CP₁	5	12	L₃₂
D_B	6	11	Q
D_A	7	10	Q
GND	8	9	A/B

Pin	Symbol	Description
1	L₂	length control input
2	L₁	length control input
3	MR	asynchronous master reset
4	CP₀	clock input (low-to-high edge-triggered)
5	CP₁	clock input (high-to-low edge-triggered)
6	D_B	data input
7	D_A	data input
8	GND	ground
9	A/B	select data input
10	Q	output
11	Q	complementary output
12	L₃₂	length input
13	L₁₆	length input
14	L₈	length input
15	L₄	length input
16	Vcc	supply voltage

Notes

The length of the shift register is determined by the sum of the length inputs (L₁, L₂, L₄, L₈, L₁₆, L₃₂) plus one.
Data is shifted in on the low-to-high transition of CP₀ when CP₁ is low, or the high-to-low transition of CP₁ when CP₀ is high.
When A/B is high, a clock pulse shifts in data from D_A. When low, a clock pulse shifts in data from D_B.
When MR is high, the register is reset, Q is forced low, and Q is forced high.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.