628128 - 128K x 8 static RAM - msarnoff.org ChipDB


NC	1 •	32	Vcc
A₁₆	2	31	A₁₅
A₁₄	3	30	CS2
A₁₂	4	29	WE
A₇	5	28	A₁₃
A₆	6	27	A₈
A₅	7	26	A₉
A₄	8	25	A₁₁
A₃	9	24	OE
A₂	10	23	A₁₀
A₁	11	22	CS1
A₀	12	21	I/O₇
I/O₀	13	20	I/O₆
I/O₁	14	19	I/O₅
I/O₂	15	18	I/O₄
GND	16	17	I/O₃

Pin	Symbol	Description
1	NC	no connection
2	A₁₆	address input
3	A₁₄	address input
4	A₁₂	address input
5	A₇	address input
6	A₆	address input
7	A₅	address input
8	A₄	address input
9	A₃	address input
10	A₂	address input
11	A₁	address input
12	A₀	address input
13	I/O₀	data input/output
14	I/O₁	data input/output
15	I/O₂	data input/output
16	GND	ground
17	I/O₃	data input/output
18	I/O₄	data input/output
19	I/O₅	data input/output
20	I/O₆	data input/output
21	I/O₇	data input/output
22	CS1	chip select (active low)
23	A₁₀	address input
24	OE	output enable (active low)
25	A₁₁	address input
26	A₉	address input
27	A₈	address input
28	A₁₃	address input
29	WE	write enable (active low)
30	CS2	chip select (active high)
31	A₁₅	address input
32	Vcc	supply voltage

Notes

Data is written when CS1 is low, CS2 is high, and WE is low.
Data is read when CS1 is low, CS2 is high, OE is low, and WE is high.
The input/output pins assume a high-impedance state if CS1 is high or CS2 is low.

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.