| Vss | 1 • | 40 | HALT |
| NMI | 2 | 39 | TSC |
| IRQ | 3 | 38 | LIC |
| FIRQ | 4 | 37 | RESET |
| BS | 5 | 36 | AVMA |
| BA | 6 | 35 | Q |
| Vcc | 7 | 34 | E |
| A0 | 8 | 33 | BUSY |
| A1 | 9 | 32 | R/W |
| A2 | 10 | 31 | D0 |
| A3 | 11 | 30 | D1 |
| A4 | 12 | 29 | D2 |
| A5 | 13 | 28 | D3 |
| A6 | 14 | 27 | D4 |
| A7 | 15 | 26 | D5 |
| A8 | 16 | 25 | D6 |
| A9 | 17 | 24 | D7 |
| A10 | 18 | 23 | A15 |
| A11 | 19 | 22 | A14 |
| A12 | 20 | 21 | A13 |
| Pin | Symbol | Description |
|---|---|---|
| 1 | Vss | ground |
| 2 | NMI | non-maskable interrupt (active low) |
| 3 | IRQ | interrupt request (active low) |
| 4 | FIRQ | fast interrupt request (active low) |
| 5 | BS | bus status output |
| 6 | BA | bus available output |
| 7 | Vcc | supply voltage |
| 8 | A0 | address bus |
| 9 | A1 | address bus |
| 10 | A2 | address bus |
| 11 | A3 | address bus |
| 12 | A4 | address bus |
| 13 | A5 | address bus |
| 14 | A6 | address bus |
| 15 | A7 | address bus |
| 16 | A8 | address bus |
| 17 | A9 | address bus |
| 18 | A10 | address bus |
| 19 | A11 | address bus |
| 20 | A12 | address bus |
| 21 | A13 | address bus |
| 22 | A14 | address bus |
| 23 | A15 | address bus |
| 24 | D7 | data bus |
| 25 | D6 | data bus |
| 26 | D5 | data bus |
| 27 | D4 | data bus |
| 28 | D3 | data bus |
| 29 | D2 | data bus |
| 30 | D1 | data bus |
| 31 | D0 | data bus |
| 32 | R/W | bus read/write |
| 33 | BUSY | busy status |
| 34 | E | clock input |
| 35 | Q | quadrature clock input |
| 36 | AVMA | advanced VMA signal (indicates bus will be used in the next cycle) |
| 37 | RESET | reset (active low) |
| 38 | LIC | last instruction cycle (high during last cycle of instruction) |
| 39 | TSC | three-state control (active high; tri-states address, data, R/W) |
| 40 | HALT | halt (active low) |
| Parameter | Value | Unit |
|---|---|---|
| Clock speed | 1 (6809E) 1.5 (68A09E) 2 (68B09E) | MHz |
| A, B | 8-bit Accumulators (can be combined into 16-bit accumulator, D) |
| X | 16-bit Index Register |
| Y | 16-bit Index Register |
| U | 16-bit User Stack Pointer |
| S | 16-bit Hardware Stack Pointer |
| PC | 16-bit Program Counter |
| DP | 8-bit Direct Page Register |
| CC | 8-bit Condition Code Register |
| E | (bit 7) | Entire machine state was stacked |
| F | (bit 6) | FIRQ inhibit flag |
| H | (bit 5) | Half-carry flag (valid only after ADC or ADD instructions) |
| I | (bit 4) | IRQ inhibit flag |
| N | (bit 3) | Negative flag (most significant bit of previous result) |
| Z | (bit 2) | Zero flag |
| V | (bit 1) | Signed two's complement overflow flag |
| C | (bit 0) | Carry flag |
| CC | (pulled first, pushed last) |
| A | |
| B | |
| DP | |
| X msb | |
| X lsb | |
| Y msb | |
| Y lsb | |
| U/S msb | |
| U/S lsb | |
| PC msb | |
| PC lsb | (pulled last, pushed first) |
| FFFE-FFFF | RESET |
| FFFC-FFFD | NMI |
| FFFA-FFFB | SWI |
| FFF8-FFF9 | IRQ |
| FFF6-FFF7 | FIRQ |
| FFF4-FFF5 | SWI2 |
| FFF2-FFF3 | SWI3 |
| FFF1-FFF1 | Reserved |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.