1.5 (68A21)
2 (68B21)
MHz | Pulse width, E low | 430 (6821) 280 (68A21) 210 (68B21) | ns |
Pulse width, E high | 450 (6821) 280 (68A21) 220 (68B21) | ns |
Min. RESET pulse length | 1 | µs |
Notes
- Port A is designed to drive CMOS logic to normal 30%/70% levels.
- Port B uses three-state NMOS buffers and requires external resistors to pull up to CMOS levels.
- Port B is capable of driving Darlingtons.
- When in output mode, a read of Port A returns the actual pin states.
- When in output mode, a read of Port B returns the contents of the output latch.
- RS=00, bit 2 of control register A=1: peripheral register A
- RS=00, bit 2 of control register A=0: data direction register A
- RS=01: control register A
- RS=10, bit 2 of control register B=1: peripheral register B
- RS=10, bit 2 of control register B=0: data direction register B
- RS=11: control register B
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.