74109

Dual J-K flip-flop with set and reset; positive-edge trigger

PDF datasheet

    
1RD1 •16Vcc
1J2152RD
1K3142J
1CP4132K
1SD5122CP
1Q6112SD
1Q7102Q
GND892Q
    
PinSymbolDescription
11RDasynchronous reset; direct input (active low)
21Jsynchronous input
31Ksynchronous input
41CPclock input (low-to-high, edge-triggered)
51SDasynchronous set; direct input (active low)
61Qtrue output
71Qcomplement output
8GNDground
92Qcomplement output
102Qtrue output
112SDasynchronous set; direct input (active low)
122CPclock input (low-to-high, active low)
132Ksynchronous input
142Jsynchronous input
152RDasynchronous reset; direct input (active low)
16Vccsupply voltage

Specifications

(typical values under recommended operating conditions, unless specified)
ParameterValueUnit
Propagation delay, nCP to nQ, nQ15 (74HC)
17 (74HCT)
ns
Propagation delay, nSD to nQ, nQ12 (74HC)
14 (74HCT)
ns
Propagation delay, nRD to nQ, nQ12 (74HC)
15 (74HCT)
ns
Maximum clock frequency75 (74HC)
61 (74HCT)
MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.