74564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
PDF datasheet
| | | |
OE | 1 • | 20 | Vcc |
D0 | 2 | 19 | Q0 |
D1 | 3 | 18 | Q1 |
D2 | 4 | 17 | Q2 |
D3 | 5 | 16 | Q3 |
D4 | 6 | 15 | Q4 |
D5 | 7 | 14 | Q5 |
D6 | 8 | 13 | Q6 |
D7 | 9 | 12 | Q7 |
GND | 10 | 11 | CP |
| | | |
Pin | Symbol | Description |
---|
1 | OE | output enable (active low) |
2 | D0 | data input |
3 | D1 | data input |
4 | D2 | data input |
5 | D3 | data input |
6 | D4 | data input |
7 | D5 | data input |
8 | D6 | data input |
9 | D7 | data input |
10 | GND | ground |
11 | CP | clock input (low-to-high, edge-triggered) |
12 | Q7 | flip-flop output |
13 | Q6 | flip-flop output |
14 | Q5 | flip-flop output |
15 | Q4 | flip-flop output |
16 | Q3 | flip-flop output |
17 | Q2 | flip-flop output |
18 | Q1 | flip-flop output |
19 | Q0 | flip-flop output |
20 | Vcc | supply voltage |
Specifications
(typical values under recommended operating conditions, unless specified)Parameter | Value | Unit |
---|
Propagation delay, CP to Qn | 15 (74HC) | ns |
Maximum clock frequency | 127 (74HC) | MHz |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.