| Q1 | 1 • | 16 | Vcc |
| Q2 | 2 | 15 | Q0 |
| Q3 | 3 | 14 | DS |
| Q4 | 4 | 13 | OE |
| Q5 | 5 | 12 | RCK |
| Q6 | 6 | 11 | SCK |
| Q7 | 7 | 10 | MR |
| GND | 8 | 9 | Q7' |
| Pin | Symbol | Description |
|---|---|---|
| 1 | Q1 | parallel data output |
| 2 | Q2 | parallel data output |
| 3 | Q3 | parallel data output |
| 4 | Q4 | parallel data output |
| 5 | Q5 | parallel data output |
| 6 | Q6 | parallel data output |
| 7 | Q7 | parallel data output |
| 8 | GND | ground |
| 9 | Q7' | serial data output |
| 10 | MR | master reset (active low) |
| 11 | SCK | shift register clock input |
| 12 | RCK | storage register latch input |
| 13 | OE | output enable (active low) |
| 14 | DS | serial data input |
| 15 | Q0 | parallel data output |
| 16 | Vcc | supply voltage |
| Parameter | Value | Unit |
|---|---|---|
| Propagation delay, SCK to Q7' | 19 (74HC) 25 (74HCT) | ns |
| Propagation delay, SCK to Qn | 20 (74HC) 24 (74HCT) | ns |
| Propagation delay, MR to Q7' | 100 (74HC) 52 (74HCT) | ns |
| Maximum clock frequency, SCK and RCK | 100 (74HC) 57 (74HCT) | MHz |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.