74597

8-bit shift register with input flip-flops


D₁	1 •	16	Vcc
D₂	2	15	D₀
D₃	3	14	D_S
D₄	4	13	PL
D₅	5	12	ST_CP
D₆	6	11	SH_CP
D₇	7	10	MR
GND	8	9	Q

Pin	Symbol	Description
1	D₁	parallel data input
2	D₂	parallel data input
3	D₃	parallel data input
4	D₄	parallel data input
5	D₅	parallel data input
6	D₆	parallel data input
7	D₇	parallel data input
8	GND	ground
9	Q	serial data output
10	MR	asynchronous master reset (active low)
11	SH_CP	shift clock input (low-to-high, edge-triggered)
12	ST_CP	storage clock input (low-to-high, edge-triggered)
13	PL	parallel load input (active low)
14	D_S	serial data input
15	D₀	parallel data input
16	Vcc	supply voltage

Specifications

(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, SH_CP to Q	17 (74HC) 20 (74HCT)	ns
Propagation delay, ST_CP to Q	25 (74HC) 29 (74HCT)	ns
Propagation delay, PL to Q	21 (74HC) 26 (74HCT)	ns
Maximum clock frequency, SH_CP	96 (74HC) 83 (74HCT)	MHz

Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.