| (RESET/dW) PA2 | 1 • | 20 | Vcc |
| (RXD) PD0 | 2 | 19 | PB7 (UCSK/SCL/PCINT7) |
| (TXD) PD1 | 3 | 18 | PB6 (MISO/DO/PCINT6) |
| (XTAL2) PA1 | 4 | 17 | PB5 (MOSI/DI/SDA/PCINT5) |
| (XTAL1) PA0 | 5 | 16 | PB4 (OC1B/PCINT4) |
| (CKOUT/XCK/INT0) PD2 | 6 | 15 | PB3 (OC1A/PCINT3) |
| (INT1) PD3 | 7 | 14 | PB2 (OC0A/PCINT2) |
| (T0) PD4 | 8 | 13 | PB1 (AIN1/PCINT1) |
| (OC0B/T1) PD5 | 9 | 12 | PB0 (AIN0/PCINT0) |
| GND | 10 | 11 | PD6 (ICP) |
| Pin | Symbol | Description |
|---|---|---|
| 1 | (RESET/dW) PA2 | reset (active low) |
| 2 | (RXD) PD0 | UART receive; port D |
| 3 | (TXD) PD1 | UART transmit; port D |
| 4 | (XTAL2) PA1 | clock oscillator pin 2; port A |
| 5 | (XTAL1) PA0 | clock oscillator pin 1; port A |
| 6 | (CKOUT/XCK/INT0) PD2 | external interrupt 0; clock output; port D |
| 7 | (INT1) PD3 | external interrupt 1; port D |
| 8 | (T0) PD4 | port D |
| 9 | (OC0B/T1) PD5 | port D |
| 10 | GND | ground |
| 11 | PD6 (ICP) | port D |
| 12 | PB0 (AIN0/PCINT0) | port B |
| 13 | PB1 (AIN1/PCINT1) | port B |
| 14 | PB2 (OC0A/PCINT2) | port B |
| 15 | PB3 (OC1A/PCINT3) | port B |
| 16 | PB4 (OC1B/PCINT4) | port B |
| 17 | PB5 (MOSI/DI/SDA/PCINT5) | 3-wire data input; 2-wire data; port B |
| 18 | PB6 (MISO/DO/PCINT6) | 3-wire data output; port B |
| 19 | PB7 (UCSK/SCL/PCINT7) | 3-wire clock; 2-wire clock; port B |
| 20 | Vcc | supply voltage |
| Parameter | Value | Unit |
|---|---|---|
| Flash memory | 2K (ATtiny2313) 4K (ATtiny4313) | bytes |
| Internal SRAM | 128 (ATtiny2313) 256 (ATtiny4313) | bytes |
| EEPROM | 128 (ATtiny2313) 256 (ATtiny4313) | bytes |
| Programmable I/O lines | 18 | |
| Maximum clock frequency | 20 | MHz |
Note: Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.